Alignment Marks in Substrate Having Through-Substrate Via (TSV)

ABSTRACT

A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No.14/586,276, entitled “Alignment Marks in Substrate HavingThrough-Substrate Via (TSV),” filed on Dec. 30, 2014, which applicationis a continuation of U.S. patent application Ser. No. 12/874,952,entitled “Alignment Marks in Substrate Having Through-Substrate Via(TSV),” filed on Sep. 2, 2010, now U.S. Pat. No. 8,928,159 issued onJan. 6, 2015, which applications are incorporated herein by reference.

BACKGROUND

In order to form three-dimensional (3D) integrated circuit structures,through-substrate vias (TSVs) are used to electrically couple front-sidefeatures to the backside features of a wafer. On the front side, theremay be interconnect structures and metal bumps, for example. On thebackside, there may be metal bumps and redistribution lines. Dual-sidealignment needs to be performed in order to accurately align thebackside features and the front-side features with each other.

Typically, the front-side features are formed on the wafer first,followed by a backside grinding to thin a silicon substrate in thewafer, until the TSVs are exposed. Front-side alignment marks areincorporated in the front-side features. The dual-side alignment isperformed from the backside using an infra-red (IR) alignment system forlocating the front-side alignment marks, wherein the infra-red lightemitted by the IR alignment system penetrates through the thinnedsilicon substrate to reach the front-side alignment marks. Backsidealignment marks are then made on the backside of the wafers by etchinginto the backside layer(s) and into the silicon substrate.

Due to the limitation of the IR alignment system, and further due to thethickness variation in the grinded silicon substrate, the accuracy ofthe dual-side alignment is low, and the misalignment may be as high asabout 2 μm.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantagesthereof, reference is now made to the following descriptions taken inconjunction with the accompanying drawings, in which:

FIGS. 1 through 7 are cross-sectional views of intermediate stages inthe manufacturing and using of alignment marks in accordance with anembodiment;

FIG. 8 illustrates a top view of a front-side alignment mark;

FIGS. 9A through 9G illustrate various alignment marks formed ofthrough-substrate vias (TSVs);

FIG. 10 illustrates a lithography mask for forming the TSVs; and

FIGS. 11A through 11D illustrate various alignment marks formed oftrench-type TSVs.

DETAILED DESCRIPTION

The making and using of the embodiments of the disclosure are discussedin detail below. It should be appreciated, however, that the embodimentsprovide many applicable inventive concepts that can be embodied in awide variety of specific contexts. The specific embodiments discussedare merely illustrative, and do not limit the scope of the disclosure.

A novel dual-side alignment mark and methods of forming the same areprovided in accordance with an embodiment. The intermediate stages ofmanufacturing the dual-side alignment marks are illustrated inaccordance with an embodiment. The variations of the embodiments arethen discussed. Throughout the various views and illustrativeembodiments, like reference numbers are used to designate like elements.

Referring to FIG. 1, wafer 2, which includes substrate 10, is provided.In an embodiment, substrate 10 is a semiconductor substrate, such as abulk silicon substrate, although it may include other semiconductormaterials such as group III, group IV, and/or group V elements.Integrated circuit devices 16, which may include transistors, may beformed at front surface 10 a of substrate 10. In alternativeembodiments, wafer 2 is an interposer or a package substrate, which maynot include active devices such as transistors therein. However, passivedevices such as transistors and capacitors may be included in wafer 2.Substrate 10 thus may be formed of a semiconductor material such assilicon or formed of a dielectric material. Interconnect structure 12including metal lines and vias formed therein is formed over substrate10, and may be electrically coupled to the integrated circuit devices.The metal lines and vias may be formed of copper or copper alloys, andmay be formed using the well-known damascene processes. Interconnectstructure 12 may include commonly known inter-layer dielectric (ILD) 11and inter-metal dielectrics (IMDs), which are formed over ILD 11.

Alignment mark 14 is formed on the front side of substrate 10, and maybe formed, for example, in the first-level metal layer (the bottom IMDlayer), although it may be formed in other-level metal layers. A topview of an exemplary alignment mark 14 is illustrated in FIG. 8.Alignment mark 14 may have different shapes other than what is shown inFIG. 8.

Through-substrate vias (TSVs) 20 are formed in substrate 10, and extendfrom front surface 10 a of substrate 10 into substrate 10. Depending onwhether TSVs 20 are formed using a via-first approach or a via-lastapproach, TSVs 20 may extend into ILD 11 that is used to cover theactive devices, but not into the IMD layers in interconnect structure12. Alternatively, TSVs 20 may penetrate through both substrate 10, ILD11, and possibly interconnect structure 12. Isolation layers 22 areformed on the sidewalls of TSVs 20, and electrically insulate therespective TSVs 20 from substrate 10. Isolation layers 22 may be formedof commonly used dielectric materials such as silicon nitride, siliconoxide (for example, tetra-ethyl-ortho-silicate (TEOS) oxide), and thelike.

TSVs 20 include functional TSVs 20A and alignment-mark TSVs 20B.Although only one alignment-mark TSV 20B is illustrated, there may be aplurality of alignment-mark TSVs 20B, as illustrated in FIGS. 9A through9G and FIGS. 11A through 11D. Functional TSVs 20A may be used toelectrically couple the conductive features on the front side ofsubstrate 10 to the conductive features on the backside of substrate 10.Alignment-mark TSVs 20B are used for aligning the features on thebackside to the features on the front side of wafer 2. Alignment-markTSVs 20B and alignment mark 14 are aligned to each other. In anembodiment, functional TSVs 20A and alignment-mark TSVs 20B are formedsimultaneously. In alternative embodiments, functional TSVs 20A andalignment-mark TSVs 20B are formed at different times by separateformation processes. Further, functional TSVs 20A may have a samediameter, a same pitch, and/or a same height as alignment-mark TSVs 20B.Alternatively, the diameter, the pitch, and/or the height of functionalTSVs 20A may be different from that of alignment-mark TSVs 20B. Metalbumps 18 may then be formed on the front side of wafer 2.

Referring to FIG. 2, wafer 2 is bonded to carrier 27, for example,through adhesive 25, which may be ultra-violet (UV) glue. Next, as shownin FIG. 3, a backside grinding is performed to remove excess portions ofsubstrate 10. An etch may further be performed to lower back surface 10b of substrate 10, so that TSVs 20 protrude above back surface 10 b.

In FIG. 4, passivation layer 24 is formed to cover back surface 10 b ofsubstrate 10 and TSVs 20. In an exemplary embodiment, passivation layer24 includes silicon nitride layer 24 a and silicon oxynitride layer 24 bover silicon nitride layer 24 a, although passivation layer 24 may beformed different materials and/or have different structures.

Next, using a patterned photo resist, portions of passivation layer 24are etched, and the ends of TSVs 20 (including functional TSVs 20A andalignment-mark TSVs 20B) are exposed. The patterned photo resist is thenremoved, resulted in a structure shown in FIG. 5. The exposedalignment-mark TSVs 20B may thus be used as alignment mark 32, which areused for the alignment in the formation of backside features such asredistribution lines (RDLs) and/or metal bumps, so that the backsidefeatures on the backside of wafer 2 may be accurately aligned todesirable positions, and aligned to front-side alignment mark 14.

FIG. 6 illustrates the formation of under-bump metallurgy (UBM) layer28, which may be blanket formed on passivation layer 24 and exposed TSVs20, for example. UBM layer 28 may be formed using sputtering or otherapplicable methods. UBM layer 28 may include a barrier layer 28 a and aseed layer 28 b on barrier layer 28 a. In some embodiments, barrierlayer 28 a includes a Ti layer, a Ta layer, a TiN layer, a TaN layer, orcombinations thereof, although other materials may also be used. In someembodiments, the seed layer 28 b includes copper.

FIG. 7 illustrates the formation of exemplary backside features on thebackside of wafer, wherein the backside features may include metallayers, metal bumps, passivation layers, micro bumps, and/or the like.In the exemplary embodiment as shown in FIG. 7, backside features 30represent metal bumps and/or redistribution lines (RDLs). It isappreciated that although one layer of metal bumps/RDLs is shown, theremay be one or more layer of RDLs, and metal bumps over and connected tothe RDLs. In an exemplary embodiment, the formation of features 30includes forming a mask (not shown) over UBM layer 28, with a portion ofUBM layer 28 exposed through openings in the mask. A plating is thenperformed to plate a conductive material into the openings to formbackside features 30. The mask is then removed, and the portions of theUBM layer 28 previously covered by the mask are etched. Alignment-markTSVs 20B are also exposed, and may be used for the alignment in theformation of additional features such as RDLs and/or metal bumps overbackside features 30.

FIGS. 9A through 9G illustrate top views of exemplary alignment marks32, each formed of a plurality of alignment-mark TSVs 20B. When theplurality of alignment-mark TSVs 20B are grouped to form alignment mark32, the plurality of alignment-mark TSVs 20B may be arranged in anrectangular region (also marked as 32) having length L and width W,wherein the rectangular region may be free from functional TSVs. LengthL and width W may be between about 50 μm and about 400 μm, and may bebetween about 100 μm and about 200 μm. Accordingly, the rectangularregion may have a top-view area smaller than about 400 μm×400 μm, orless than about 200 μm×200 μm.

In FIGS. 9A through 9G, alignment-mark TSVs 20B may be arranged asdifferent patterns. For example, in FIGS. 9A and 9F, alignment-mark TSVs20B are aligned to lines 36A and 36B that cross each other. In FIGS. 9B,9C, and 9G, alignment-mark TSVs 20B are aligned to lines 38A and 38Bthat terminate at common points 40. FIGS. 9D and 9E illustrate otherexemplary patterns.

FIG. 10 illustrates an exemplary lithography mask 33 for forming TSVs20, wherein alignment mark patterns 32′ are formed in lithography mask33 along with patterns 20A′ for forming functional TSVs 20.Alignment-mark patterns 32′ define the patterns of alignment-mark TSVs20B, while patterns 20A′ define the patterns of functional TSVs 20A.

FIGS. 11A through 11D illustrate alternative embodiments in whichalignment marks 32 are formed of trench-type TSVs 20B, which, instead ofhaving circular top-view shapes, may have other shapes including, butare not limited to, rectangles, crosses, and combinations thereof.Trench-type TSVs 20B may be formed at the same time as, or at differenttimes than, forming functional TSVs 20A. Similarly, trench-type TSVs 20Balso penetrate through substrate 10.

By using the embodiments, alignment marks may be formed at the same timefunctional TSVs are formed. Therefore, the cost incurred in conventionalalignment-mark formation processes, including forming a photo resist fordefining the patterns of backside alignment marks on the backside ofwafer 2, etching wafer 2 for forming the backside alignment marks, andstripping off the photo resist is saved. Further, the accuracy forforming the alignment marks is improved. In conventional alignment markformation techniques, the misalignment may be as great as about 2 μm.While in the embodiments, the misalignment is reduced to less than 1 μm.

In an embodiment, a device includes: a substrate having a first surfaceand a second surface opposite the first surface; an interconnectadjacent the first surface of the substrate; a plurality of conductivefeatures adjacent the second surface of the substrate; a plurality offirst through-substrate vias (TSVs) extending from the first surface ofthe substrate to the second surface of the substrate, the first TSVselectrically connecting the conductive features to the interconnect; anda first alignment mark including a plurality of second TSVs extendingfrom the first surface of the substrate to the second surface of thesubstrate, the second TSVs being electrically isolated from theconductive features and the interconnect, the second TSVs being disposedin an alignment mark region of the substrate, the alignment mark regionbeing free from the first TSVs.

In some embodiments of the device, the alignment mark region of thesubstrate has a length of between about 50 μm and about 400 μm, and thealignment mark region of the substrate has a width of between about 50μm and about 400 μm. In some embodiments of the device, a first subsetof the second TSVs are disposed along a first axis, and a second subsetof the second TSVs are disposed along a second axis, the first axis andthe second axis being parallel to the second surface of the substrate.In some embodiments of the device, the first axis intersects the secondaxis at first point disposed at a center of the alignment mark region.In some embodiments of the device, the first axis intersects the secondaxis at a first point disposed offset from a center of the alignmentmark region. In some embodiments of the device, the interconnectincludes a second alignment mark, the second alignment mark beingaligned to the first alignment mark. In some embodiments of the device,the first TSVs and the second TSVs have the same top-view shape. In someembodiments of the device, the first TSVs and the second TSVs havedifferent top-view shapes. In some embodiments of the device, the firstTSVs and the second TSVs have the same width. In some embodiments of thedevice, the first TSVs and the second TSVs have the same height. In someembodiments of the device, the substrate is free from active devices.

In an embodiment, a device includes: a substrate having a first surfaceand a second surface opposite the first surface; an interconnect on thefirst surface of the substrate, the interconnect including conductivefeatures disposed in dielectric layers; a passivation layer on thesecond surface of the substrate; a first through-substrate via (TSV)extending through the passivation layer and the substrate, the first TSVbeing electrically connected to the conductive features of theinterconnect; a redistribution line (RDL) on the passivation layer andthe first TSV, the RDL being electrically connected to the first TSV;and a second TSV extending through the passivation layer and thesubstrate, the second TSV being electrically isolated from the RDL andthe conductive features of the interconnect.

In some embodiments of the device, the second TSV has a first endcontacting one of the dielectric layers of the interconnect. In someembodiments of the device, the passivation layer has an opening exposinga second end of the second TSV. In some embodiments of the device, thefirst TSV and the second TSV extend through the passivation layer andthe substrate by the same distance. In some embodiments of the device,the substrate is free from active devices.

In an embodiment, a device includes: a substrate having a first regionand a second region; an interconnect on a first surface of thesubstrate; a passivation layer on a second surface of the substrate; aplurality of first through-substrate vias (TSVs) extending through thepassivation layer and the first region of the substrate, the secondregion of the substrate being free from the first TSVs, the first TSVsbeing electrically connected to the interconnect; and a plurality ofsecond TSVs extending through the passivation layer and the secondregion of the substrate, the first region of the substrate being freefrom the second TSVs, the second TSVs being electrically isolated fromthe interconnect.

In some embodiments, the device further includes: a plurality ofconductive features on the first TSVs, the first TSVs being electricallyconnected to the conductive features, the second TSVs being electricallyisolated from the conductive features. In some embodiments of thedevice, the first TSVs and the second TSVs extend through thepassivation layer and the substrate by the same distance. In someembodiments of the device, the substrate is free from active devices.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A device comprising: a substrate having a firstsurface and a second surface opposite the first surface; an interconnectadjacent the first surface of the substrate; a plurality of conductivefeatures adjacent the second surface of the substrate; a plurality offirst through-substrate vias (TSVs) extending from the first surface ofthe substrate to the second surface of the substrate, the first TSVselectrically connecting the conductive features to the interconnect; anda first alignment mark comprising a plurality of second TSVs extendingfrom the first surface of the substrate to the second surface of thesubstrate, the second TSVs being electrically isolated from theconductive features and the interconnect, the second TSVs being disposedin an alignment mark region of the substrate, the alignment mark regionbeing free from the first TSVs.
 2. The device of claim 1, wherein thealignment mark region of the substrate has a length of between about 50μm and about 400 μm, and the alignment mark region of the substrate hasa width of between about 50 μm and about 400 μm.
 3. The device of claim1, wherein a first subset of the second TSVs are disposed along a firstaxis, and a second subset of the second TSVs are disposed along a secondaxis, the first axis and the second axis being parallel to the secondsurface of the substrate.
 4. The device of claim 3, wherein the firstaxis intersects the second axis at first point disposed at a center ofthe alignment mark region.
 5. The device of claim 3, wherein the firstaxis intersects the second axis at a first point disposed offset from acenter of the alignment mark region.
 6. The device of claim 1, whereinthe interconnect comprises a second alignment mark, the second alignmentmark being aligned to the first alignment mark.
 7. The device of claim1, wherein the first TSVs and the second TSVs have the same top-viewshape.
 8. The device of claim 1, wherein the first TSVs and the secondTSVs have different top-view shapes.
 9. The device of claim 1, whereinthe first TSVs and the second TSVs have the same width.
 10. The deviceof claim 1, wherein the first TSVs and the second TSVs have the sameheight.
 11. The device of claim 1, wherein the substrate is free fromactive devices.
 12. A device comprising: a substrate having a firstsurface and a second surface opposite the first surface; an interconnecton the first surface of the substrate, the interconnect comprisingconductive features disposed in dielectric layers; a passivation layeron the second surface of the substrate; a first through-substrate via(TSV) extending through the passivation layer and the substrate, thefirst TSV being electrically connected to the conductive features of theinterconnect; a redistribution line (RDL) on the passivation layer andthe first TSV, the RDL being electrically connected to the first TSV;and a second TSV extending through the passivation layer and thesubstrate, the second TSV being electrically isolated from the RDL andthe conductive features of the interconnect.
 13. The device of claim 12,wherein the second TSV has a first end contacting one of the dielectriclayers of the interconnect.
 14. The device of claim 13, wherein thepassivation layer has an opening exposing a second end of the secondTSV.
 15. The device of claim 12, wherein the first TSV and the secondTSV extend through the passivation layer and the substrate by the samedistance.
 16. The device of claim 12, wherein the substrate is free fromactive devices.
 17. A device comprising: a substrate having a firstregion and a second region; an interconnect on a first surface of thesubstrate; a passivation layer on a second surface of the substrate; aplurality of first through-substrate vias (TSVs) extending through thepassivation layer and the first region of the substrate, the secondregion of the substrate being free from the first TSVs, the first TSVsbeing electrically connected to the interconnect; and a plurality ofsecond TSVs extending through the passivation layer and the secondregion of the substrate, the first region of the substrate being freefrom the second TSVs, the second TSVs being electrically isolated fromthe interconnect.
 18. The device of claim 17 further comprising: aplurality of conductive features on the first TSVs, the first TSVs beingelectrically connected to the conductive features, the second TSVs beingelectrically isolated from the conductive features.
 19. The device ofclaim 17, wherein the first TSVs and the second TSVs extend through thepassivation layer and the substrate by the same distance.
 20. The deviceof claim 17, wherein the substrate is free from active devices.